Practical Jsc Limits for SHJ Devices: Insights From Modelling
DOI:
https://doi.org/10.52825/siliconpv.v1i.943Keywords:
Silicon Heterojunction, Solar Cell, Short-Circuit Current Density, Ray Tracing, ModellingAbstract
Modern industrial silicon heterojunction (SHJ) solar cells are increasingly limited by the short-circuit current density (Jsc) and there is a strong interest in understanding how much novel approaches such as window layers, novel transparent conductive oxides (TCOs) and anti-reflection coatings (ARCs) could improve the Jsc of SHJ solar cells. In this work, the practical Jsc limits of SHJ solar cells are determined using a carefully calibrated ray-tracing model, validated using empirical data from in-house solar cells as well as recently published high-efficiency front-and-back contacted (FAB) SHJ solar cells. The model is then further refined to obtain a detailed Jsc loss breakdown of the latest record efficiency FAB SHJ solar cells, for which there are no published Jsc loss breakdowns. Notable advances made in these advanced solar cells with regards to window layers, TCOs and ARCs at the cell level are analysed. Based on the magnitude of impact on the solar cell Jsc, the most critical factors for achieving high-Jsc SHJ solar cells are identified and ranked. Allowing for additional improvements and combining the best approaches identified, an estimate of the practical upper limit of Jsc for FAB SHJ solar cells is determined to be 41.81 mA/cm2. This work serves as a useful reference for the current state of play for Jsc improvements in SHJ solar cells, and highlights practical pathways and issues for improving commercial SHJ solar cells.
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Copyright (c) 2024 Erik M. Spaans, Selvaraj Venkataraj, Armin G. Aberle, Nitin Nampalli
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National Research Foundation Singapore
Grant numbers I1801E0027 -
Agency for Science, Technology and Research
Grant numbers I1801E0027
